1. Field of the Invention
The present invention relates to semiconductor packaging, and more particularly to semiconductor package devices and their methods of manufacture and testing.
2. Description of the Related Art
In the field of electronic systems, there is a continuous need to increase performance and reduce size. This is largely achieved by improving semiconductor wafer manufacturing and semiconductor packaging technologies. Wafer manufacturing involves simultaneously fabricating numerous semiconductor chips as a batch on a silicon wafer using various etching, doping and depositing steps. After the wafer is complete, the chips are separated from one another and packaged.
Wafer manufacturing strives to reduce transistor or capacitor feature size in order to increase circuit density and enhance functionality. Device geometries with sub-micron line widths are so common that individual chips routinely contain millions of electronic devices. Reduced feature size has been quite successful in improving electronic systems, and continuous development is expected in the future. However, significant obstacles to further reduction in feature size are being encountered. These obstacles include defect density control, optical system resolution limits, and availability of processing material and equipment. Attention has therefore increasingly shifted to semiconductor packaging as a means to fulfill the relentless demands for enhanced system performance.
Semiconductor chips have input/output pads that must be connected to external circuitry in order to function as part of an electronic system. Traditionally, a single chip is individually housed in a single-chip package that is connected to other single-chip packages through a printed circuit board (or motherboard) which supplies power to the chips and provides signal routing among the chips. The single-chip package has connection media that is typically an array of metallic leads (e.g., a lead frame) or a support circuit (e.g., a substrate).
Several connection techniques are widely used for connecting the chip pads and the connection media. These include wire bonding, tape automated bonding (TAB) and flip-chip bonding. Wire bonding is by far the most common. In this approach, wires are bonded, one at a time, from the chip to external circuitry by thermocompression, thermosonic or ultrasonic processes. TAB involves bonding gold-bumped pads on the chip to external circuitry on a polymer tape using thermocompression bonding. TAB requires mechanical force such as pressure or a burst of ultrasonic vibration and elevated temperature to accomplish metallurgical welding between the wires or bumps and the designated surface. Flip-chip bonding involves providing pre-formed solder bumps on the pads, flipping the chip so that the pads face down and are aligned with and contact matching bond sites, and melting the solder bumps to wet the pads and the bond sites. After the solder reflows it is cooled down and solidified to form solder joints between the pads and the bond sites. Many variations exist on these basic methods.
A major advantage of flip-chip bonding over wiring bonding and TAB is that it provides shorter connection paths between the chip and the external circuitry, and therefore has better electrical characteristics such as less inductive noise, cross-talk, propagation delay and waveform distortion. In addition, flip-chip bonding requires minimal mounting area and weight which results in overall cost saving since no extra packaging and less circuit board space are used. While flip-chip technology has tremendous advantages over wire bonding and TAB, its cost and technical limitations are significant. For instance, the cost of forming bumps on the pads is significant. An adhesive is normally underfilled between the chip and the support circuit to reduce stress on the solder joints due to thermal mismatch between the chip and the support circuit, and the underfilling process increases both manufacturing complexity and cost. The solder joints exhibit increased electrical resistance as well as cracks and voids over time due to fatigue from thermo-mechanical stresses. Further, the solder is typically a tin-lead alloy and lead-based materials are becoming far less popular due to environmental concerns over disposing of toxic materials and leaching of toxic materials into ground water supplies. Thus, none of these conventional connection techniques are entirely satisfactory.
Conventional single-chip packages typically have an area (or footprint) that is many times larger than the area of the chip, causing the printed circuit board to have excessively large area relative to the chips. However, as chip speeds increase, it becomes critical to position the chips close together since excessive signal transmission distance deteriorates signal integrity and propagation times. Other considerations such as manufacturing cost, reliability, heat transfer, moisture resistance, mounting and interconnect standardization, testability, and quality control have also become focal points of chip packaging.
Single-chip packages such as thin small outline packages (TSOPs) and ball grid arrays (BGAs) have been developed to address these considerations. TSOPs include an insulative housing that encapsulates the chip and rows of leads that protrude from opposing side surfaces of the insulative housing and are bent to provide distal end portions that are coplanar with or extend below the bottom surface of the insulative housing. The leads are connected to the chip pads in one-to-one relation. BGAs include a substrate with a top surface upon which the chip is mounted, an insulative housing that encapsulates the chip, and an array of balls that protrude from the bottom surface of the substrate. The balls are connected to the chip pads in one-to-one relation.
TSOPs and BGAs provide certain advantages but they have disadvantages as well. For instance, TSOPs are fairly compact but the leads can require significantly larger area than the chip. Thus, TSOPs tend to occupy more surface area than BGAs. BGAs, on the other hand, can be more difficult to test than TSOPs since the balls are less easily inserted into and removed from a test socket than are TSOP leads. Furthermore, standard TSOP test sockets are readily available, whereas the balls are often configured to match the electrical contact arrangement on the printed circuit board in the next level assembly. As a result, a customized test socket may be needed to match the balls. Moreover, TSOP and BGA packages often employ wire bonding, TAB or flip-chip bonding, and as mentioned above, none of these chip pad connection techniques are entirely satisfactory.
In view of the various development stages and limitations in currently available semiconductor package devices, there is a need for a semiconductor package device that is cost-effective, reliable, manufacturable, provides excellent mechanical and electrical performance, and is flexible enough to accommodate test sockets and printed circuit boards with different contact terminal arrangements.
An object of the present invention is to provide a semiconductor package device that provides a low cost, high performance, high reliability package. Another object of the present invention is to provide a convenient, cost-effective method of making a semiconductor package device. Still another object of the present invention is to provide a method of testing a semiconductor package device.
Generally speaking, the present invention provides a semiconductor package device with terminals that protrude downwardly from the bottom surface of an insulative housing and leads that protrude laterally from the side surfaces of the insulative housing. The terminals and leads are connected together and to the chip pads in one-to-one relation. As a result, the leads can be inserted into a test socket that need not contact the terminals, and the terminals can be mounted on a printed circuit board that need not contact the leads.
In accordance with one aspect of the invention, a semiconductor package device includes an insulative housing, a semiconductor chip, a terminal and a lead, wherein the insulative housing includes a top surface, a bottom surface, and a peripheral side surface between the top and bottom surfaces, the chip includes a conductive pad, the terminal protrudes downwardly from and extends through the bottom surface and is electrically connected to the pad, the lead protrudes laterally from and extends through the side surface and is electrically connected to the pad, the terminal and the lead are spaced and separated from one another outside the insulative housing, and the terminal and the lead are electrically connected to one another inside the insulative housing and outside the chip.
Preferably, the insulative housing includes a first single-piece housing portion that contacts the chip and the lead and is spaced from the terminal, and a second single-piece housing portion that contacts the first single-piece housing portion and the terminal, such that the first housing portion provides the top surface, the side surface and a peripheral portion of the bottom surface, and the second housing portion provides a central portion of the bottom surface within the peripheral portion of the bottom surface.
It is also preferred that the peripheral portion of the bottom surface is shaped as a rectangular peripheral ledge that extends a first distance below the central portion of the bottom surface, the terminal extends a second distance below the central portion of the bottom surface, and the first distance is greater than the second distance.
It is also preferred that the device includes multiple terminals arranged as an array that protrudes downwardly from and extends through the bottom surface of the insulative housing, the device includes multiple leads arranged as TSOP leads that protrude laterally from and extend through opposing side surfaces of the insulative housing, the chip includes multiple conductive pads, and each of the terminals is electrically connected to one of the leads and one of the pads within the insulative housing and outside the chip.
It is also preferred that the device is devoid of wire bonds, TAB leads and solder joints.
In accordance with another aspect of the invention, a method of making a semiconductor package device includes attaching a semiconductor chip to a metallic structure using an insulative adhesive, wherein the chip includes a conductive pad, the metallic structure includes first and second opposing surfaces and a lead, the adhesive is disposed between the first surface and the chip, the lead includes a recessed portion, a non-recessed portion and opposing outer edges between the first and second surfaces that extend across the recessed and non-recessed portions, and the recessed portion is recessed relative to the non-recessed portion at the second surface, forming an encapsulant that contacts the chip, the first surface, the outer edges and the recessed portion, wherein the encapsulant completely covers the chip, the outer edges and the recessed portion without completely covering the non-recessed portion, and forming a connection joint that electrically connects the lead and the pad.
Preferably, the outer edges are defined by slots in the metallic structure, the recessed portion and the slots are formed by selectively etching the metallic structure, the recessed portion is fully formed and the slots are partially formed by selectively etching the metallic structure from the second surface towards the first surface, and the slots are partially formed by selectively etching the metallic structure from the first surface towards the second surface.
It is also preferred that the encapsulant contacts an entire side of the chip opposite the pad, fills the recessed portion and is coplanar with the non-recessed portion at the second surface.
It is also preferred that the encapsulant forms a first insulative housing portion, and a second insulative housing portion is subsequently formed that contacts the adhesive, the terminal and the first insulative housing portion, such that the first and second insulative housing portions form an insulative housing the surrounds the chip.
It is also preferred that the first insulative housing portion is formed by transfer molding and the second insulative housing portion is formed without transfer molding.
In accordance with another aspect of the invention, a method of testing a semiconductor package device includes providing a device that includes an insulative housing, a semiconductor chip, a terminal and a lead, wherein the chip includes a conductive pad, the terminal protrudes downwardly from and extends through a bottom surface of the housing, the lead protrudes laterally from and extends through a side surface of the housing, and the terminal and the lead are electrically connected to one another and the pad inside the insulative housing, attaching the device to a test socket that electrically contacts the lead without electrically contacting the terminal, testing the device using the test socket, and removing the device from the test socket.
Preferably, the method includes trimming the lead after removing the device from the test socket and then attaching the device to a printed circuit board that electrically contacts the terminal without electrically contacting the lead.
It is also preferred that the method includes bending the lead at two corners to provide a TSOP lead with a distal end outside the top and bottom surfaces and then trimming the lead so that the lead no longer extends outside the top and bottom surfaces.
It is also preferred that the method includes trimming the insulative housing and the lead using a laser to shrink the insulative housing and remove the lead.
It is also preferred that the method includes trimming the insulative housing and the lead to convert the device into a chip scale package.
An advantage of the semiconductor package device of the present invention is that it is reliable, cost-effective, easily manufacturable, and can be directly mounted on a printed circuit board. Another advantage is that the device need not include wire bonds, TAB leads or solder joints. Another advantage is that the encapsulant provides a single-piece housing portion that can surround and interlock the leads. Another advantage is that each chip pad is electrically connected to a terminal and a lead, thereby allowing the leads to match a test socket for testing the device and allowing the terminals to match a printed circuit board for the next level assembly. As a result, the device is flexible enough to accommodate test sockets and printed circuit boards with different electrical contact arrangements. Another advantage is that the device can be trimmed after testing the device using the leads and before connecting the device to a printed circuit board using the terminals, thereby converting the device from a TSOP package to a grid array package that provides a chip scale package. Another advantage is that the device can be manufactured using low temperature processes which reduces stress and improves reliability. A further advantage is that the device can be manufactured using well-controlled processes which can be easily implemented by circuit board, lead frame and tape manufacturers. Still another advantage is that the device can be manufacture using materials that are compatible with copper chip and lead-free environmental requirements.
These and other objects, features and advantages of the invention will be further described and more readily apparent from a review of the detailed description of the preferred embodiments which follows.